Version 2.1 - December 17, 2018
     * Localization update
     * Fix segfault on exit
     * Partial fix for whitespace in filenames
     * Fix showing of pictures and using style in documentation
     * Add manuals about circuits 74xx for all languages
     * Gettext support for messages, examples, tutorials
     * Partially cygwin support

Version 2.1-a1 - June 19, 2015
     * Verga can parse output drive strengths for gates
     * Corrected tri0 and tri1 net signals with only 1 drive in Verga
     * Pullup and pulldown elements added, thus P-MOP and N-MOP
         transistor level circuits are allowed

Version 2.0.0 - June 19, 2015
     * Very few changes

Version 2.0-rc3 - March 16, 2015
     * Fixed regression, introduced in 2.0-rc2, causing segmentation
       fault after synchronization of the module interface

Version 2.0-rc2 - March 11, 2015
     * Fixed bug, causing the LEDs and switches of the same name,
       placed in different modules, be incorrectly redrawed
     * Fixed bugs, related with 64-bit architectures
     * Fixed bug in JK flip-flop primitive (Set/Reset invertion)
     * Fixed display and write system tasks for  output decimal values with
       high-impedance and unknown bits according to the unit 17.1.1.4 of
       IEEE 1364-2001 in Verga.
     * A lot of build warnings fixed and workarounded.

Version 2.0-rc1 - February 27, 2015
     * 74xx library extended: added circuits
         7411 triple input AND
         7420 Quad input NAND
         7421 Quad input AND
         7442 BCD decoder
         7447 BCD to 7-segment encoder
         74181 4-bit ALU
         74182 Carry look ahead unit
     * Added russian locale
     * Some additional messages and settings (including license text)
       now can be localized
     * Fixed bug in ROM primitive causing it was unable to set the
       high-impedance output value when OE input is zero
     * Fixed bug in 74154 (incorrect name of output register)
     * Fixed bug, causing incorret locale encoding settings not handled
       properly
     * Fixed a lot of bugs, related with the usage of uninitialized
       values, invalid reads and writes, memory leaks in tkgate and verga
     * Fixed division by zero bug
     * Fixed build scripts to allow build from sources on newer Linux
       systems and OpenBSD
     * Fixed bug causing the library circuit parameters to override the
       main circuit ones
     * Fixed erratums and grammar error
     * Unlocked the hidden pancake recipe

Version 2.0-b10 - September 26, 2009
     * Fixed bug causing bar led to display wrong value when some bits are unknown.
     * Fixed bug making "Add" button inactive in port list dialog box for
	concat components.
     * Fixed bug in memory viewer for memories with 256 words or less.
     * Fixed bug causing initialization file specs. on memories not to
	be recognized.

Version 2.0-b9 - May 5, 2009
     * Fixed bug causing core dump when reversing port ordering on decoder.
     * Fixed bug in updating module tree when creating module instances.
     * Expanded components in the 74xx library.

Version 2.0-b8 - April 25, 2009
     * Fixed bug with libraries with no descriptions.
     * Fixed bug in freeing of memory in circuit properties editing
       which caused a core dump on some systems.
     * Fixed bug in module interface update when loading a module that
	overrides a library module of the same name.
     * Fixed bug in display of scope axis when non-standard timescale
	is used.

Version 2.0-b7 - February 23, 2009
     * Wire names can be displayed on switches/dips
     * Right click on wires now sensitive to label/size markings.
     * Added ability to supress timing violation notices.
     * Fixed bug causing excessive calls to html formatter in comments objects.

Version 2.0-b6 - February 12, 2009
     * Created new "Scripts" tab in Circuit Properties dialog box. Moved list
	of start-up scripts to the new page.
     * Moved the "Auto Start" option from the "General" page to the "Simulation"
	page in the Circuit Properties box.
     * Added a "Design Initialization Time" circuit property that can specify
	a time over which to ignore timing violations.

Version 2.0-b6 - February 6, 2009
     * Fixed detection of iconv.h
     * Fixed Japanese font problem in tk elements.
     * Fixed bugs with wire handling, library handling, simulation error handling.
     * Fixed bug with switches not updating in GUI when controlled by script.
     * Updated "Details" pages of several gate properties dialog boxes.
     * Improved handling of locales
     * Tabbing in dialog boxes added
     * Reorganized main menus
     * Renamed DEMUX as DECODER. Added a properly defined DEMUX.
     * Updated most of the Japanese locale strings
     * Updated all German locale strings and tutorials
     * Added JK Flip-Flop
     * Added "Script" component that allows you to include Verilog snippets in
	netlist modules.
     * Added memory content viewer
     * Added "current time" display when simulator is active.

Version 2.0-b5 - Internal Only

Version 2.0-b4 - January 10, 2009
     * Fixed core dump bug caused by clicking in scope window below list
       of traces.
     * Cleaned up interface look.
     * Fixed sizing problem with dialog boxes that sometimes caused clipping
       of the dialog box elements.
     * Fixed simulator bug in register initialization. Registers were not
       being initialized until end of time step 0 and were triggering events.
     * Fixed problem with initial display of flip-flop type in properties
       dialog box.
     * Updated gmac to produce new-style memory files (-g can be used to
       get old-style files).
     * Fixed problem with entries in port box not getting highlighted when clicked on.
     * Fixed memory problem that happens when doing "new circuit" from menu.
     * Fixed bug with module copy/rename, etc. dialog boxes not going away on "OK"
     * Fixed bug with rename of currently viewed module.
     * Dialog titlebars now localizable.

Version 2.0-b3 - January 2, 2009
     * Grab and scroll tool (and auto grab with button 2)
     * New options setting dialog box
     * Mouse over highlighting for tabs
     * Wires with bit sizes greater than 32 bits
     * Fixed bug with warning reporting in simulation mode
     * Updated print dialog box
     * Updated library manager and added it to the circuit properies box
     * Fixed problem with display of Japanese in main edit window.
     * Additional minor bug fixes.

Version 2.0-b2 - December 22, 2008
     * Fixed problem with leds in modules
     * Fixed edge problem with ranges in scope window
     * Fixed display problem with scope print dialog box
     * Fixed problem with saving of wire merge devices
     * Fixed some problems with unnecessary setting of "modified" flag
     * Probe positions now remembered between simulation runs
     * You can now drag and reposition traces in scope.
     * Mouse over of signal names in scope will show full name.
     * Fixed simulator bug when assigning concat to a variable with
	a bit width larger than the source.

Version 2.0-b1 - December 1, 2008
     * Updated to work with tcl/tk 8.5
     * Fixed bug in flip-flop device.
     * Create verilog template system for built-in devices (see primitives directory)
     * Fixed bug in "Delete Module" dialog box causing core dump when dialog
       was closed by pressing enter.

Version 2.0-a12 - September 24, 2007
     * Cleanup of some names in menus.
     * Added key bindings for interface update features.

Version 2.0-a11 - September 24, 2007
     * Fixed bugs and made minor feature enhancements to block port editing
       through popup menus.
     * Fixed bug causing delayed updates to graphical view in interface editor
     * Module instances can now be updated in place with new interfaces.
     * Slight redesign of the module interface type selector.

Version 2.0-a10 - September 19, 2007
     * Added mouse-over cursor change on edges of blocks.
     * Fixed problems with port names changing when wire is cut.
     * When connecting wires, oldest name is now given precedence
       in making name choice for merged wire.
     * Fixed problem with getting module edge popup menu when window has
       been scrolled.

Version 2.0-a9 - September 12, 2007
     * Fixed configure script to look in /opt/local for Tcl/Tk
     * Fixed bit-order problem in display of symbol modules on some platforms.
     * Fixed start-up crash on 64-bit machines.
     * Fixed bug in symbol editor that could cause loss of port information
     * Implement import/export of X bitmaps in symbol editor

Version 2.0-a8 - August 18, 2007
     * Fixed problem preventing hyperlinks from working when num-lock/scroll-lock
       was pressed.
     * Changed default install directory to /usr/local on all machines
     * Minor interface tweeks.

Version 2.0-a7 - August 17, 2007
     * Changed default install directory to /usr/local on non-FreeBSD machines.
     * Fixed some printing bugs
     * Fixed bugs with print dialog box
     * Fixed bug with display of gate name on "concat" elements
     * Fixed configuration problem with Italian locale
     * Ability to force TTY input from simulation script added.

Version 2.0-a6 - July 13, 2007
     * Made wire taps easier to select.
     * Fixed bug in layout of module interfaces.
     * Fixed bug allowing wires to be inappropriately manipulated in the interface display.
     * Initial draft of documentation for 2.0

Version 2.0-a5 - May 22, 2007
     * Autoconf-based installation
     * Fixed bug preventing the shift-click sequence from being able to edit hyperlinks
     * Fixed some Japanese localization issues.

Version 2.0-a1 - February 7, 2007
     * Updated interface.
     * Support for textual Verilog module definitions.
     * All gates are now rotatable. Use Tab/Backtab to rotate selection.
     * Automatic interface generator.
     * Support for user defined symbols.
     * Hierarchical module browser.
     * Jump-to-module supported while in simulation mode.
     * Expanded and dockable toolbars.
     * Better library support.
     * Pinout options on concat, muxes, and demuxes.

Version 1.8.4 - May 25, 2004
     * Added memory of probes between invocations of the simulator.
     * Improved command-line printing capabilities.
     * Fixed a bug that resulted in a compilation error when compiling under
	a gcc version less than 3.0.
     * Fixed a bug that caused spurious warnings when printing a circuit
	directly from the command line.
     * Fixed another problem with EPSF output.
     * Fixed a bug with the critical path analysis of an empty circuit.
     * Fixed coding problem with Japanese messages file.
     * Fixed bug causing potential simulator core dump in critical path
	computation.

Version 1.8.3 - March 18, 2004
     * Fixed a bug occuring when creating or editing a comment after editing
       the ports on another circuit element.
     * Modules now printed in "hierarchical" order.
     * Updated German support and reorganized localization files.
     * Configure script now looks for MAC OS X directories.
     * Configure script is now more cygwin friendly.
     * Empty comments are no longer invisible.

Version 1.8.2 - February 12 , 2004
     * Fixed bug when loading library from command line.
     * Fixed bug when printing selected modules.
     * Fixed bug with '-V' circuit verify command.
     * Fixed bug in Edit menu with Algn Vert. and Algn Horz. being swapped.
     * Fixed bug with cut/paste of concat elements at 90/270 degree orientations.
     * Fixed bug with undo of wire taps.
     * Fixed bug with simulator error reporting.

Version 1.8.1 - January 19, 2004
     * Fixed bug occurring when clocks are used to drive adders.
     * Fixed bug with printing of partial scope traces.
     * Fixed bug in undo from edit module interface screen.
     * Added toolbar on scope window.
     * Added a "crosshair" feature to scopes.
     * Added a right-click selection capability on scopes for selecting print range.
     * Added capability to suppress sorting of traces on scope.

Version 1.8 - January 7, 2004
     * Fixed multiple bugs in the undo/redo code.
     * Updated toolbar icons and changed the behavior of the toolbar to be context sensitve.
     * Fixed compatability problems with tcl/tk 8.4.
     * Fixed printing problem with wire merge elements.
     * Fixed problem with very long clock cycle times.
     * Fixed problem with EPSF output.

Version 1.7 - February 5, 2002
      * Added multi-undo/-redo function.
      * Current technology of gates are now visible through popup menu.
      * Fixed bug allowing changes to anchor flag of gates in library modules.
      * Fixed bug occuring when doing "Edit Interfaces..." while currently
	editing a library module.

Version 1.6i - February 5, 2002
      * Added extender bars on multi-input (more than 2) AND, OR and XOR
	gates to avoid "crunching" of wires for gates with many inputs.
	This feature is off by default when loading save files for earlier
	versions of tkgate unless explicitly enabled.
      * Fixed problem with using some right mouse button popup commands
	when zoomed.
      * Increased delay between a mouse press and hold on a signal and the
	pop-up showing the signal value while in simulation mode. The previous
	short delay interfered with detection of a double click on some systems
	and thus made it difficult to set probes. It now also possible to
	customize this delay through the simulator page on options dialogue box.
      * Disabled bug allowing net options to be modified while in simulator mode.
      * Added alternate probe set/remove command using 'P' keyboard shortcut
	or menu.
      * Initial support for "hierarchy graph" for Postscript output added. This
	support is currently limited to graphs that fit on a single page.
      * Fixed several bugs that could sometimes cause a core dump and/or
	save file corruption when manipulating "wire tap" elements.
      * Fixed bug that sometimes resulted in a failure to determine the direction
	of concat (wire merge) elements.
      * Fixed a bug that caused calloc() to be called with nmemb=0.
      * Marked various popups as transient so they would not get buried under
	the main window.
      * Changed port add/editing so that an "*unnamed*" signal will be assigned
	a standard generated name.
      * Fixed bugs with port on editing through properties dialog box on modules.
      * Fixed problem with panic save feature. The panic save feature causes
	tkgate to attempt to save the current circuit in PANIC.v if a core dump
	is detected.
      * Produces less confusing messages when running under an unsupported locale.

Version 1.6h - June 11, 2001
      * Fixed printing problems with dips, muxes and registers.
      * Fixed Japanese in menus and tutorials.
      * Added bit selection feature for register codes to gmac.
      * Made '\r' a valid whitespace character.
      * Fixed bug that allowed creation of meaningless inverters on wire taps.
      * Fixed core dump bug with "replicating" wire taps.
      * Fixed serious problem with cut/paste causing internal data structures
	and save file data to become corrupt. The problem occured when gates
	attached to the same net were included in the cut, but one or more of
	the joints/taps on the net were not included in the cut causing a
	partitioning of the net.
      * Added a data structure integrity check feature.

Version 1.6g - February 6, 2001
      * Added zoom in/out feature.
      * Fixed core dump caused by start-up time errors on some platforms.
      * Fixed core dump caused by loading out-dated tkgate file while flashing
        critical path option is enabled.
      * Improved commenting of macrocode in "menagerie" example.
      * Minor change to scrollbar semantics

Version 1.6f - November 30, 2000
      * Fixed incorrect installation of Japanese tutorials.
      * Japanese Translation of tutorials partially completed.
      * Added support for Spanish.
      * Fixed problem with dialog windows being lowered when opening
        a subordinate load/save file box.
      * Fixed problem with setting label on frames.

Version 1.6e - November 16, 2000
      * Fixed problem with memories with less than 8-bit data lines.
      * Fixed possible direction problem with wire merge.

Version 1.6d - October 19, 2000
      * Fixed carry-out on 32-bit adders
      * Postscript generator now uses latin1 encoding to enable correct
	printing of accented characters.
      * Dip switch "value" boxes are now closed when exiting the simulation.
      * Fixed Japanese configure problem.

Version 1.6c - October 16, 2000
      * Improved multi-lingual support.
      * Added French support.

Version 1.6b - October 4, 2000
      * Fixed possible core dump problem when deleting gates.
      * Fixed configuration script problems.

Version 1.6 - September 27, 2000
      * Experimental support for critical path analysis
      * Highlighting of selected net
      * Smooth scrolling in edit window
      * Added a seprated "D flip-flop" element.
      * -P and -p switch allow printing without starting the GUI.
      * Fixed problem with non-functional output inverters on several gate types
	including registers, rams, roms and ttys.
      * Fixed hang problem with simulator when root module not at top of module stack.
      * Fixes problem with adding outputs to decoders.
      * Fixes extraneous "unknown version" messages when loading old save files.
      * Fixes problem with externally generated "destroy" events on scope windows.

Version 1.5c - September 8, 2000
      * Fixes an intermittent core dump problem in editor when manipulating wires.
      * Fixes problem with inverters in postscript output.
      * Fixes problem with configuration file in detecting existance of bison.

Version 1.5b - June 27, 2000

      * Fixes core dump problem in simulator.

      * Fixes possible core dump in editor when exiting simulator.

Version 1.5 - June 26, 2000
      * Support for multiple gate 'technologies' and per-gate delay
	specification added.

      * Menu and shortcut internals updated. Shortcuts and menus for gate
	definitions now contained in the gate definition files. This is a
	precursor to supporting user-definiable primitives. The new shortcut
	definition method allows keyboard shortcuts to be defined in .tkgaterc
	file.

      * Better recovery from syntax errors in input files.

      * Accedental editing of library modules disabled. An explicit "Claim"
        command was added to convert library modules to user modules.

      * Bug fixes
           - fixed slopy gate label positions

           - fixed slopy delete of mux/demux

           - fixed position of input numbers on mux/demux

           - fixed corruption of internal data structures when doing a
	     cut/paste in Edit Interface page

           - fixed core dump when opeing "Edit Interfaces" while simulation was
             active (now disabled while in simulation mode).

           - fixed possible save file corruption due to null net names.

           - fixed multiple module instances on the Edit Interfaces page.

           - fixed erroneous setting of 'modified' flag when opening Edit
	     Interfaces page.

	   - fixed memory initialization problem in gsim causing periodic
	     simulator crashes.

           - moved "Circuit Properties" command from "Module" menu to "Edit" menu.

      * NOTE: Save files from tkgate 1.5 may not be readable under earlier
        versions of tkgate if you use the new delay specification features.

Version 1.4c - June 12, 2000
      * Fixed Postscript output and bit tap problems (Applied patch tkgate-1.4b.patch1)

      * Added Postscript output of Japanese (works for printers with Japanese fonts only).

      * Made ports on modules easier to select.

      * Fixed problem with changing port type in external port dialog box.

Version 1.4b - June 7, 2000
      * Fixed the library module problem (applied tkgate-1.4.patch1)

      * Fixed problems with Japanese input

      * Created a seperate directory for Japanese tutorials. Selection of the
        tutorial directory depends on the selected interface language. Currently
        only a small portion of the tutorial have been translated.

Version 1.4 - June 2, 2000
      * Added LED devices (single bit, bar graph, 7-segment)

      * Added context sensitive popup menus (bound to right mouse button)

      * Added "add wire segment" feature to attach new wire segments in
        the middle of existing wires.

      * Bug fix (Simulator crashed when circuit contained anchored modules)

      * Bug fix (States of switches in modules sometimes not shown properly
        when there are multiples instances of that module)

      * Bug fix (Various objects still created with default name even
        when hitting 'cancel' in dialog box).

      * Bug fix (Y2K problem in Postscript output)

      * Bug fix (Connecting wires of different bit widths caused core dump)

Verion 1.3b - May 4, 2000
      * Fixed minor problem with compiling in some versions of Linux

      * Improved commenting in the Menagerie CPU example.

      * Fixed bug in editing comments (comment not saved when closing dialog box
	by hitting return in hyperlink entry box).

Verion 1.3 - April 20, 2000
      * Microcode/macrocode compiler (gmac) now generates a human readable symbol map.

      * Better delay model

      * Multi-lignual features added (English and Japanese)

      * Hyperlink comments

      * Improved tutorial (using hyperlinks)

      * Added 'zoom' command to simulator script to set zoom factor on scope.

Version 1.2b - April 13, 2000
      * Fixed problems with SunOS 5.7

Version 1.2 - April 13, 2000
      * Hit test for gates now works better for long thin gates such as registers

      * Problem with deleting ports on primitive gates fixed

      * Horizontal/Vertical alignment feature added (see "Edit" menu)

Version 1.1 - March 31, 2000
      * Color interface implemented.

      * Smooth scrolling in scope implemented.

      * Fixed bugs under Solaris (SunOS 5.5)

      * Fixed verious other bugs.

Version 1.0 - March 22, 2000
      * Fixed bugs.

Version 0.9 - May 28, 1999
      * Initial public release.

